1. Field of the Invention
The present invention relates to error detection and, more particularly, to methods and systems of detecting transfer errors in an address bus.
2. Description of the Related Art
Microprocessors include a hierarchy of memory subsystems. FIG. 1 is a simplified block diagram of a conventional microprocessor with memory subsystems. As shown in FIG. 1, central processing unit (CPU) core 100 is connected to memory subsystems by address buses 106 and data buses 108. The memory subsystems include level 2 on-chip cache 102 for storing data that require low access latency and larger off-chip main memories 104 for storing data that require high access bandwidths.
Transfers of data from CPU core 100 to and from the memory subsystems through data buses 108 are typically protected by Error Correction Code (ECC). However, transfer of memory addresses through address buses 106 are not protected. Adding parity protection to address buses 106 is becoming increasingly important because the sizes of the memory subsystems are increasing rapidly or more memory subsystems are connected to CPU core 100. As a result, address buses 106 are also increasing in size. Larger address buses are more prone to transfer errors because more memory addresses are transferred. Transfer errors may result from electronic noise, faulty wires, electro-migration problems, and poor electrical connections, and the transfer errors cause data to be accessed from and written to incorrect memory addresses. Adding parity protection to address buses 106 normally requires adding a dedicated parity bit to the memory address that results in additional pins. However, a memory module with additional pins cannot plug into existing memory sockets. Adding parity protection to address buses 106 is thus not feasible with existing hardware systems.
In view of the foregoing, there is a need for adding parity protection to the address buses while maintaining existing pin-compatibility.